1. Field of the Invention
The present invention relates to a film deposition apparatus and a film deposition method for depositing a film on a substrate by alternately supplying plural reaction gases to a substrate, allowing the reaction gases to react with each other on the substrate, and thus depositing a film formed of a reaction product on the substrate.
2. Description of the Related Art
Along with further miniaturization of circuit patterns in semiconductor devices, various films that constitute the semiconductor devices are demanded to be thinner and more uniform. As a film deposition method capable of responding such demand, a so-called Atomic Layer Deposition (ALD) or Molecular Layer Deposition (MLD) has been drawing attention (for example, Patent Document 1). In such a film deposition method, a first reaction gas is adsorbed on a surface of a semiconductor wafer (referred to as a wafer hereinafter) under vacuum and then a second reaction gas is adsorbed on the surface of the wafer in order to form one or more atomic or molecular layers through reaction of the first and the second reaction gases on the surface of the wafer; and such an alternating adsorption of the gases is repeated plural times, thereby depositing a film on the wafer. This method is advantageous in highly uniform thickness distribution, highly accurate thickness controllability, and excellent gap-filling characteristic, because the reaction gases can be adsorbed on the wafer in a (quasi-)self-limiting manner.
Patent Document 1: Japanese Patent Application Laid-Open Publication No. 2010-56470.
Patent Document 2: Japanese Patent Application Laid-Open Publication No. 2003-142484.
However, because aspect ratios of a trench for a trench isolation structure and a space of a line-and-space pattern tend to be larger along with further miniaturization of the circuit patterns, it becomes difficult to fill the trench and the space even by the ALD method. For example, when a space having a width of 30 nm is filled with silicon oxide, a film thickness tends to be greater at an upper end part of side walls of the space than at a bottom part of the space, because reaction gases cannot easily proceed toward the bottom part. As a result, a void may be caused in the silicon oxide that fills the space. In this case, when the silicon oxide is etched in the subsequent process step, an opening may be formed in the upper part of the silicon oxide, so that the opening is in communication with the void. If this happens, an etching agent used in the etching process step may flow into the void through the opening, so that the etching agent having flowed into the void may cause contamination in subsequent processes. Alternatively, in a subsequent metallization step, metal may enter the void through the opening of the silicon oxide, so that the metal causes defects.
Such a problem may be caused not only in the ALD method but also in a chemical vapor deposition (CVD) method. For example, when a connection hole formed in a semiconductor substrate is filled with an electrically conductive material thereby forming an electrical connection (i.e., a plug), a void may be caused in the plug. In order to avoid such voids, there has been proposed a method where an over hang part that is formed of the electrically conductive material at an upper part of the connection hole is etched repeatedly while the electrically conductive material is intermittently deposited on the substrate, so that the plug without the void can be obtained (Patent Document 2).